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Codenamed Prescott New Instructions, or PNI, SSE3 is the third iteration of the SSE SIMD Instruction Set, created by Intel ro rival AMD's 3DNow! instruction sets.

The earlier SIMD sets on the x86 platform, from oldest to newest, are MMX, 3DNow! (used only by AMD), SSE and SSE2.

Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. AMD introduced SSE3 in the Revision E of their Athlon 64 CPUs, released in April 2005.

SSE3 adds about 13 new instructions to its predecessor, SSE2. The most notable addition is the capability to work horizontally in a register, as opposed to the more or less strictly vertical operation of all previous SSE instructions. More specifically, instructions to add and subtract horizontally in a register have been added. These instructions simplify the implementation of a number of DSP and 3D operations.

SSE3 also includes a set of Instructions related to HyperThreading. AMD have left out two instructions from the SSE3 instruction set, the FXSAVE FXRSTOR instructions.

These are the instructions added:

  • FISTTP
  • ADDSUBPS
  • ADDSUBPD
  • MOVSLDUP
  • MOVSHDUP
  • MOVDDUP
  • LDDQU
  • HADDPS
  • HSUBPS
  • HADDPD
  • HSUBPD
  • MONITOR
  • MWAIT

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